1. Field of the Invention
This invention relates to a semiconductor device, specifically to a charge pump device with large current capacity used for a power supply circuit. Performance of the charge pump device can be improved and a latch up can be prevented with this invention.
2. Description of the Related Art
Video equipment in recent years such as a camcorder, a digital still camera (DSC) and a mobile phone with DSC use CCDs (charge-coupled devices) to capture an image. A CCD drive circuit for driving the CCDs requires a power supply circuit that provides both positive and negative high voltages (over 10 volts) and a large current (several milliamperes). A switching regulator is used for that purpose today.
The switching regulator can generate a high voltage with high performance, i.e. with high power efficiency (output power/input power). However, it has a drawback to generate a harmonic noise when switching a current. Therefore, the power supply has to be used with a noise shield. In addition to that, it requires a coil as an external part.
Consequently, a Dickson charge pump device has come to attention as a power supply circuit for portable equipment described above. The Dickson charge pump device is described in detail in a technical journal xe2x80x9cJohn F. Dickson xe2x80x98On-chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Techniquexe2x80x99, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.SC-11, No.3, pp.374-378, Jun. 1976xe2x80x9d, for example.
FIG. 18 shows a circuit diagram of a four-stage Dickson charge pump device. Diodes D1-D5 are connected in series. Each of coupling capacitors C1-C4 is connected to each of connecting nodes between the diodes D1-D5. CL refers to an output capacitor. CLK and CLKB are input clock pulses having opposite phase to each other. The CLK and CLKB are inputted to a clock driver 51. A numeral 52 refers to a current load. The clock driver 51 is provided with a power supply voltage Vdd. Herewith, an output amplitude of the clock pulses "PHgr"1 and "PHgr"2 outputted from the clock driver 51 becomes Vdd. The clock pulse "PHgr"1 is fed to the capacitors C2 and C4, while the clock pulse "PHgr"2 is fed to the capacitors C1 and C3.
In a stable state, in which a constant current Iout flows out, an input current to the charge pump device is a sum of a current from an input voltage Vin and a current provided from the clock driver. These currents are as described below, disregarding charging/discharging currents to/from stray capacitors. During a period of "PHgr"1=High and "PHgr"2=Low, an average current of 2 Iout flows through each of paths in directions depicted in the figure as solid line arrows.
During a period of "PHgr"1=Low and "PHgr"2=High, an average current of 2 Iout flows through each of paths in directions depicted in the figure as dashed line arrows. An average current of each of these currents over a clock cycle is Iout. A boosted voltage from the charge pump device in the stable state is expressed by an equation (1),
Vout=Vinxe2x88x92Vd+n(Vxcfx86xe2x80x2xe2x88x92V1xe2x88x92Vd)xe2x80x83xe2x80x83(1)
where Vxcfx86xe2x80x2 refers to an amplitude of a voltage at each of the connecting nodes induced through the coupling capacitor by a change in the clock pulse; V1 denotes a voltage drop due to the output current Iout; Vin denotes the input voltage, which is usually set at Vdd in positive voltage boosting and at 0V in negative voltage boosting; Vd refers to a forward bias diode voltage; and n denotes a number of stages of pumping. Furthermore, V1 and Vxcfx86xe2x80x2 are expressed by following equations,
V1=Iout/(f(C+Cs))=(2Iout T/2)/(C+Cs)xe2x80x83xe2x80x83(2)
Vxcfx86xe2x80x2=Vxcfx86C/(C+Cs)xe2x80x83xe2x80x83(3)
where C1-C4 denote clock coupling capacitances; Cs denotes a stray capacitance at each of the connecting nodes; Vxcfx86 denotes the amplitude of the clock pulses; f denotes a frequency of the clock pulses; and T denotes a clock period of the clock pulses. Power efficiency of the charge pump device is expressed by following equation, disregarding charging/discharging currents from/to the clock driver to/from the stray capacitors and assuming Vin=Vdd.
xcex7=VoutIout/((n+1)Vdd Iout)=Vout/((n+1)Vdd)xe2x80x83xe2x80x83(4)
In this way, the charge pump device boosts the voltage by successively transferring electric charge to a next stage using a diode as a charge transfer device. However, an MOS transistor is easier than a PN junction diode to implement in a semiconductor integrated circuit because of compatibility of the manufacturing process.
For this reason, using MOS transistors as the charge transfer devices in place of the diodes D1-D5 has been proposed. In this case, Vd in the equation (1) is replaced with Vth representing a threshold voltage of the MOS transistor.
The inventors have investigated applying the charge pump device to a power supply circuit. The inventors have found following issues.
The first issue is to reduce ON resistance of a charge transfer MOS transistor, so that the charge pump circuit can provide a high voltage (over 10V) and a large current (several milliamperes) required to the power supply circuit.
The second issue is to prevent a latch up, which often happens to a high current charge pump device. Especially, there has been a problem with a large current charge pump device to cause a latch up at the beginning of the operation. The mechanism of the latch up based on the investigation made by the inventors will be described hereinafter.
FIG. 20 is a cross-sectional view showing a charge pump device implemented in a CMOS structure.
The structure shown in the cross-sectional view corresponds to that of the charge transfer MOS transistors M2 and M3 shown in FIG. 19. Separate P-type well regions 31 and 32 are formed in an N-type well region 20 formed in a surface of a P-type semiconductor substrate 10. And the charge transfer MOS transistor M2 is formed in the P-type well region 31. The charge transfer MOS transistor M3 is formed in the P-type well region 32.
Detailed explanation on the charge transfer MOS transistor M2 formed in the P-type well region 31 is given hereinafter. A drain layer D and a source layer S, both of which are N+-type, are formed in the surface of the P-type well region 31. P+ layers 41, having higher impurity concentration than the P-type well region 31, are formed in the P-type well region 31. The drain layer D and the P+ layers 41 are electrically connected with an aluminum interconnection or the like.
Since the drain D of the charge transfer transistor M2 and the P-type well region 31, in which the charge transfer MOS transistor M2 is formed, are electrically connected through low resistance, an increase in a threshold voltage Vth of the charge transfer transistor M2 due to a back gate effect is surely prevented. The charge transfer transistor M3 formed in the P-type well region 32 is structured similarly. Also, other charge transfer transistors M1, M4 and M5, which are not shown in the figure, are structured similarly.
By providing the N-type well region 20 with the boosted output voltage Vout from the charge pump device, the N-type well region 20 is reverse biased against the P-type well regions 31 and 32 in a steady state.
However, it has turned out that when the P-type well regions 31 and 32 are formed in a single N-type well region 20 as described above, a phenomenon like a latch up occurs and the output voltage Vout is hardly boosted. The inventors estimate the cause of the occurrence of the phenomenon as described below.
First, a parasitic thyristor is formed between the neighboring P-type well regions 31 and 32. That is, a vertical NPN transistor Tr1 and a lateral PNP transistor Tr2 are formed as shown in FIG. 20, where an emitter of the vertical NPN transistor Tr1 is made of the drain layer D of the charge transfer MOS transistor M2, a base of the Tr1 is made of the P-type well region 31 and a collector of the Tr1 is made of the N-type well region 20.
Also, an emitter of the lateral PNP transistor Tr2 is made of a P+ layer 42 formed in the P-type well region 32, a base of Tr2 is made of the N-type well region 20 between the P-type well regions 31 and 32 and a collector of Tr2 is made of the P-type well region 31. The parasitic NPN transistor Tr1 and the parasitic PNP transistor Tr2 compose the parasitic thyristor.
Following inequalities hold when the charge pump device shown in FIG. 19 is in a steady operation,
output voltage Vout greater than V3 greater than V2 greater than V1 greater than input voltage Vin
where the input voltage Vin is normally Vdd (equal to the power supply voltage to the clock driver); V3 denotes a voltage of the source of the charge transfer MOS transistor M3; V2 denotes a voltage of the source of the charge transfer MOS transistor M2; and V1 denotes a voltage of the source of the charge transfer MOS transistor M1.
However, following inequalities hold at start-up of the charge pump device (at the beginning of the voltage boosting).
V1 greater than V2 greater than V3 greater than Vout
That is, the capacitors C1, C2, C3 and C4 are sequentially charged beginning from the first stage.
Consequently, a current flows between the emitter and the base of the parasitic PNP transistor Tr2, when it turns to be V1xe2x88x92Vout greater than VF. That is to say, the parasitic NPN transistor Tr2 turns on. VF refers to a turn-on voltage between the base and the emitter.
Since a collector current of the parasitic PNP transistor Tr2 makes a base current of the parasitic NPN transistor Tr1, the parasitic NPN transistor Tr1 turns on herewith, and conduction begins between the emitter and the collector of the Tr1. Then, the parasitic NPN transistor Tr1 provides the parasitic PNP transistor Tr2 with base-emitter current, while it causes a current from the output voltage Vout to the voltage V1.
As a result, the output voltage Vout is not boosted. The joint operation between the parasitic transistors Tr1 and Tr2 described above is called a latch up.
A waveform chart at the beginning of the operation of the charge pump device obtained by a simulation is shown in FIG. 21. V1 denotes a drain voltage of the charge transfer MOS transistor M2, and V2 denotes a drain voltage of the charge transfer MOS transistor M3. The NPN transistor Tr1 turns on to induce the latch up, when Vds, a voltage between the source and the drain, exceeds VF (=0.7V approximately).
This invention can solve the issues addressed above, and can provide a semiconductor device structure suitable for a charge pump device with large current capacity and high efficiency.
The latch up can be prevented and the stable operation can be realized with this invention.
The semiconductor device of this invention includes a single crystalline semiconductor substrate of a first conductivity type, an epitaxial semiconductor layer of a second conductivity type grown on the single crystalline semiconductor substrate, a well region of the first conductivity type formed in the epitaxial semiconductor layer, a first buried layer of the first conductivity type abutting on a bottom of the well region of the first conductivity type, a second buried layer of the second conductivity type partially overlapping with the first buried layer of the first conductivity type and electrically isolating the well region of the first conductivity type from the single crystalline semiconductor substrate and an MOS transistor formed in the well region of the first conductivity type.
With a configuration described above, the first buried layer of the first conductivity type reduces a resistance of the well region and robustness against latch up can be enhanced. And the well region of the first conductivity can be set at desired potential independent from the single crystalline semiconductor substrate because of the second buried layer of the second conductivity type.
And with the configuration described above, a back gate bias effect of the MOS transistor can be suppressed when the drain layer of the MOS transistor and the well region of the first conductivity are electrically connected.